/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-12-27 15:24:15
 *
 */


#ifndef AON_CLK_CORE_H
#define AON_CLK_CORE_H

#define CTL_BASE_AON_CLK_CORE 0x402D0200


#define REG_AON_CLK_CORE_CGM_EMC_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0020 )
#define REG_AON_CLK_CORE_CGM_AON_APB_CFG          ( CTL_BASE_AON_CLK_CORE + 0x0024 )
#define REG_AON_CLK_CORE_CGM_ADI_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0028 )
#define REG_AON_CLK_CORE_CGM_AUX0_CFG             ( CTL_BASE_AON_CLK_CORE + 0x002C )
#define REG_AON_CLK_CORE_CGM_AUX1_CFG             ( CTL_BASE_AON_CLK_CORE + 0x0030 )
#define REG_AON_CLK_CORE_CGM_AUX2_CFG             ( CTL_BASE_AON_CLK_CORE + 0x0034 )
#define REG_AON_CLK_CORE_CGM_PROBE_CFG            ( CTL_BASE_AON_CLK_CORE + 0x0038 )
#define REG_AON_CLK_CORE_CGM_PWM0_CFG             ( CTL_BASE_AON_CLK_CORE + 0x003C )
#define REG_AON_CLK_CORE_CGM_PWM1_CFG             ( CTL_BASE_AON_CLK_CORE + 0x0040 )
#define REG_AON_CLK_CORE_CGM_PWM2_CFG             ( CTL_BASE_AON_CLK_CORE + 0x0044 )
#define REG_AON_CLK_CORE_CGM_EFUSE_CFG            ( CTL_BASE_AON_CLK_CORE + 0x0048 )
#define REG_AON_CLK_CORE_CGM_SP_UART0_CFG         ( CTL_BASE_AON_CLK_CORE + 0x004C )
#define REG_AON_CLK_CORE_CGM_SP_UART1_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0050 )
#define REG_AON_CLK_CORE_CGM_32K_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0054 )
#define REG_AON_CLK_CORE_CGM_1K_CFG               ( CTL_BASE_AON_CLK_CORE + 0x0058 )
#define REG_AON_CLK_CORE_CGM_THM_CFG              ( CTL_BASE_AON_CLK_CORE + 0x005C )
#define REG_AON_CLK_CORE_CGM_AUD_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0060 )
#define REG_AON_CLK_CORE_CGM_AUDIF_CFG            ( CTL_BASE_AON_CLK_CORE + 0x0064 )
#define REG_AON_CLK_CORE_CGM_VBC_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0068 )
#define REG_AON_CLK_CORE_CGM_CPU_DAP_CFG          ( CTL_BASE_AON_CLK_CORE + 0x006C )
#define REG_AON_CLK_CORE_CGM_CPU_DAP_MTCK_CFG     ( CTL_BASE_AON_CLK_CORE + 0x0070 )
#define REG_AON_CLK_CORE_CGM_CPU_TS_CFG           ( CTL_BASE_AON_CLK_CORE + 0x0074 )
#define REG_AON_CLK_CORE_CGM_AUD_IIS_DA0_CFG      ( CTL_BASE_AON_CLK_CORE + 0x0078 )
#define REG_AON_CLK_CORE_CGM_AUD_IIS0_AD0_CFG     ( CTL_BASE_AON_CLK_CORE + 0x007C )
#define REG_AON_CLK_CORE_CGM_AUD_IIS1_AD0_CFG     ( CTL_BASE_AON_CLK_CORE + 0x0080 )
#define REG_AON_CLK_CORE_CGM_RTC4M0_REF_CFG       ( CTL_BASE_AON_CLK_CORE + 0x0084 )
#define REG_AON_CLK_CORE_CGM_RTC4M0_FDK_CFG       ( CTL_BASE_AON_CLK_CORE + 0x0088 )
#define REG_AON_CLK_CORE_CGM_DJTAG_TCK_CFG        ( CTL_BASE_AON_CLK_CORE + 0x008C )
#define REG_AON_CLK_CORE_CGM_SP_AHB_CFG           ( CTL_BASE_AON_CLK_CORE + 0x0090 )
#define REG_AON_CLK_CORE_CGM_CA5_TS_CFG           ( CTL_BASE_AON_CLK_CORE + 0x0094 )
#define REG_AON_CLK_CORE_CGM_FUNCDMA_CFG          ( CTL_BASE_AON_CLK_CORE + 0x0098 )
#define REG_AON_CLK_CORE_CGM_EMC_REF_CFG          ( CTL_BASE_AON_CLK_CORE + 0x009C )
#define REG_AON_CLK_CORE_CGM_CSSYS_CFG            ( CTL_BASE_AON_CLK_CORE + 0x00A0 )
#define REG_AON_CLK_CORE_CGM_DET_32K_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00A4 )
#define REG_AON_CLK_CORE_CGM_PMU_CFG              ( CTL_BASE_AON_CLK_CORE + 0x00A8 )
#define REG_AON_CLK_CORE_CGM_26M_PMU_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00AC )
#define REG_AON_CLK_CORE_CGM_TMR_CFG              ( CTL_BASE_AON_CLK_CORE + 0x00B0 )
#define REG_AON_CLK_CORE_CGM_HW_I2C_CFG           ( CTL_BASE_AON_CLK_CORE + 0x00B4 )
#define REG_AON_CLK_CORE_CGM_SP_I2C0_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00B8 )
#define REG_AON_CLK_CORE_CGM_SP_I2C1_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00BC )
#define REG_AON_CLK_CORE_CGM_SP_SPI0_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00C0 )
#define REG_AON_CLK_CORE_CGM_POWER_CPU_CFG        ( CTL_BASE_AON_CLK_CORE + 0x00C4 )
#define REG_AON_CLK_CORE_CGM_AP_AXI_CFG           ( CTL_BASE_AON_CLK_CORE + 0x00C8 )
#define REG_AON_CLK_CORE_CGM_SDIO0_2X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00CC )
#define REG_AON_CLK_CORE_CGM_SDIO0_1X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00D0 )
#define REG_AON_CLK_CORE_CGM_SDIO1_2X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00D4 )
#define REG_AON_CLK_CORE_CGM_SDIO1_1X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00D8 )
#define REG_AON_CLK_CORE_CGM_SDIO2_2X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00DC )
#define REG_AON_CLK_CORE_CGM_SDIO2_1X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00E0 )
#define REG_AON_CLK_CORE_CGM_EMMC_2X_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00E4 )
#define REG_AON_CLK_CORE_CGM_EMMC_1X_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00E8 )
#define REG_AON_CLK_CORE_CGM_NANDC_2X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00EC )
#define REG_AON_CLK_CORE_CGM_NANDC_1X_CFG         ( CTL_BASE_AON_CLK_CORE + 0x00F0 )
#define REG_AON_CLK_CORE_CGM_DPU_CFG              ( CTL_BASE_AON_CLK_CORE + 0x00F4 )
#define REG_AON_CLK_CORE_CGM_DPU_DPI_CFG          ( CTL_BASE_AON_CLK_CORE + 0x00F8 )
#define REG_AON_CLK_CORE_CGM_DSI_RXESC_CFG        ( CTL_BASE_AON_CLK_CORE + 0x00FC )
#define REG_AON_CLK_CORE_CGM_DSI_LANEBYTE_CFG     ( CTL_BASE_AON_CLK_CORE + 0x0100 )
#define REG_AON_CLK_CORE_CGM_WCDMA_CFG            ( CTL_BASE_AON_CLK_CORE + 0x0104 )
#define REG_AON_CLK_CORE_CGM_OTG_REF_CFG          ( CTL_BASE_AON_CLK_CORE + 0x0108 )
#define REG_AON_CLK_CORE_CGM_CPHY_CFG_CFG         ( CTL_BASE_AON_CLK_CORE + 0x010C )
#define REG_AON_CLK_CORE_CGM_DPHY_REF_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0110 )
#define REG_AON_CLK_CORE_CGM_DPHY_CFG_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0114 )
#define REG_AON_CLK_CORE_CGM_DSI_TEST_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0118 )
#define REG_AON_CLK_CORE_CGM_RFTI_SBI_CFG         ( CTL_BASE_AON_CLK_CORE + 0x011C )
#define REG_AON_CLK_CORE_CGM_RFTI1_XO_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0120 )
#define REG_AON_CLK_CORE_CGM_RFTI_LTH_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0124 )
#define REG_AON_CLK_CORE_CGM_RFTI2_XO_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0128 )
#define REG_AON_CLK_CORE_CGM_LVDSRF_CALI_CFG      ( CTL_BASE_AON_CLK_CORE + 0x012C )
#define REG_AON_CLK_CORE_CGM_SERDES_DPHY_APB_CFG  ( CTL_BASE_AON_CLK_CORE + 0x0130 )
#define REG_AON_CLK_CORE_CGM_SERDES_DPHY_REF_CFG  ( CTL_BASE_AON_CLK_CORE + 0x0134 )
#define REG_AON_CLK_CORE_CGM_SERDES_DPHY_CFG_CFG  ( CTL_BASE_AON_CLK_CORE + 0x0138 )
#define REG_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG    ( CTL_BASE_AON_CLK_CORE + 0x013C )
#define REG_AON_CLK_CORE_CGM_DJTAG_TCK_HW_CFG     ( CTL_BASE_AON_CLK_CORE + 0x0140 )
#define REG_AON_CLK_CORE_CGM_GPU_CORE_CFG         ( CTL_BASE_AON_CLK_CORE + 0x0144 )
#define REG_AON_CLK_CORE_CGM_GPU_SOC_CFG          ( CTL_BASE_AON_CLK_CORE + 0x0148 )
#define REG_AON_CLK_CORE_CGM_WCN_CFG              ( CTL_BASE_AON_CLK_CORE + 0x014C )
#define REG_AON_CLK_CORE_CGM_MM_EMC_CFG           ( CTL_BASE_AON_CLK_CORE + 0x0150 )
#define REG_AON_CLK_CORE_CGM_MM_AHB_CFG           ( CTL_BASE_AON_CLK_CORE + 0x0154 )
#define REG_AON_CLK_CORE_CGM_BPC_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0158 )
#define REG_AON_CLK_CORE_CGM_DCAM_IF_CFG          ( CTL_BASE_AON_CLK_CORE + 0x015C )
#define REG_AON_CLK_CORE_CGM_ISP_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0160 )
#define REG_AON_CLK_CORE_CGM_JPG_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0164 )
#define REG_AON_CLK_CORE_CGM_CPP_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0168 )
#define REG_AON_CLK_CORE_CGM_SENSOR0_CFG          ( CTL_BASE_AON_CLK_CORE + 0x016C )
#define REG_AON_CLK_CORE_CGM_SENSOR1_CFG          ( CTL_BASE_AON_CLK_CORE + 0x0170 )
#define REG_AON_CLK_CORE_CGM_SENSOR2_CFG          ( CTL_BASE_AON_CLK_CORE + 0x0174 )
#define REG_AON_CLK_CORE_CGM_MM_VSP_EMC_CFG       ( CTL_BASE_AON_CLK_CORE + 0x0178 )
#define REG_AON_CLK_CORE_CGM_MM_VSP_AHB_CFG       ( CTL_BASE_AON_CLK_CORE + 0x017C )
#define REG_AON_CLK_CORE_CGM_VSP_CFG              ( CTL_BASE_AON_CLK_CORE + 0x0180 )
#define REG_AON_CLK_CORE_CGM_GPU_CORE_FRA_DIV     ( CTL_BASE_AON_CLK_CORE + 0x0184 )
#define REG_AON_CLK_CORE_CGM_GPU_SOC_FRA_DIV      ( CTL_BASE_AON_CLK_CORE + 0x0188 )

/* REG_AON_CLK_CORE_CGM_EMC_CFG */

#define BIT_AON_CLK_CORE_CGM_EMC_CFG_CGM_EMC_SEL(x)                       (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_AON_APB_CFG */

#define BIT_AON_CLK_CORE_CGM_AON_APB_CFG_CGM_AON_APB_DIV(x)               (((x) & 0x3) << 8)
#define BIT_AON_CLK_CORE_CGM_AON_APB_CFG_CGM_AON_APB_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_ADI_CFG */

#define BIT_AON_CLK_CORE_CGM_ADI_CFG_CGM_ADI_SEL(x)                       (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_AUX0_CFG */

#define BIT_AON_CLK_CORE_CGM_AUX0_CFG_CGM_AUX0_DIV(x)                     (((x) & 0xF) << 8)
#define BIT_AON_CLK_CORE_CGM_AUX0_CFG_CGM_AUX0_SEL(x)                     (((x) & 0x1F))

/* REG_AON_CLK_CORE_CGM_AUX1_CFG */

#define BIT_AON_CLK_CORE_CGM_AUX1_CFG_CGM_AUX1_DIV(x)                     (((x) & 0xF) << 8)
#define BIT_AON_CLK_CORE_CGM_AUX1_CFG_CGM_AUX1_SEL(x)                     (((x) & 0x1F))

/* REG_AON_CLK_CORE_CGM_AUX2_CFG */

#define BIT_AON_CLK_CORE_CGM_AUX2_CFG_CGM_AUX2_DIV(x)                     (((x) & 0xF) << 8)
#define BIT_AON_CLK_CORE_CGM_AUX2_CFG_CGM_AUX2_SEL(x)                     (((x) & 0x1F))

/* REG_AON_CLK_CORE_CGM_PROBE_CFG */

#define BIT_AON_CLK_CORE_CGM_PROBE_CFG_CGM_PROBE_DIV(x)                   (((x) & 0xF) << 8)
#define BIT_AON_CLK_CORE_CGM_PROBE_CFG_CGM_PROBE_SEL(x)                   (((x) & 0x1F))

/* REG_AON_CLK_CORE_CGM_PWM0_CFG */

#define BIT_AON_CLK_CORE_CGM_PWM0_CFG_CGM_PWM0_SEL(x)                     (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_PWM1_CFG */

#define BIT_AON_CLK_CORE_CGM_PWM1_CFG_CGM_PWM1_SEL(x)                     (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_PWM2_CFG */

#define BIT_AON_CLK_CORE_CGM_PWM2_CFG_CGM_PWM2_SEL(x)                     (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_EFUSE_CFG */

#define BIT_AON_CLK_CORE_CGM_EFUSE_CFG_CGM_EFUSE_SEL                      BIT(0)

/* REG_AON_CLK_CORE_CGM_SP_UART0_CFG */

#define BIT_AON_CLK_CORE_CGM_SP_UART0_CFG_CGM_SP_UART0_DIV(x)             (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_SP_UART0_CFG_CGM_SP_UART0_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SP_UART1_CFG */

#define BIT_AON_CLK_CORE_CGM_SP_UART1_CFG_CGM_SP_UART1_DIV(x)             (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_SP_UART1_CFG_CGM_SP_UART1_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_32K_CFG */


/* REG_AON_CLK_CORE_CGM_1K_CFG */


/* REG_AON_CLK_CORE_CGM_THM_CFG */

#define BIT_AON_CLK_CORE_CGM_THM_CFG_CGM_THM_SEL                          BIT(0)

/* REG_AON_CLK_CORE_CGM_AUD_CFG */

#define BIT_AON_CLK_CORE_CGM_AUD_CFG_CGM_AUD_SEL                          BIT(0)

/* REG_AON_CLK_CORE_CGM_AUDIF_CFG */

#define BIT_AON_CLK_CORE_CGM_AUDIF_CFG_CGM_AUDIF_SEL(x)                   (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_VBC_CFG */

#define BIT_AON_CLK_CORE_CGM_VBC_CFG_CGM_VBC_SEL                          BIT(0)

/* REG_AON_CLK_CORE_CGM_CPU_DAP_CFG */

#define BIT_AON_CLK_CORE_CGM_CPU_DAP_CFG_CGM_CPU_DAP_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_CPU_DAP_MTCK_CFG */


/* REG_AON_CLK_CORE_CGM_CPU_TS_CFG */

#define BIT_AON_CLK_CORE_CGM_CPU_TS_CFG_CGM_CPU_TS_SEL(x)                 (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_AUD_IIS_DA0_CFG */


/* REG_AON_CLK_CORE_CGM_AUD_IIS0_AD0_CFG */


/* REG_AON_CLK_CORE_CGM_AUD_IIS1_AD0_CFG */


/* REG_AON_CLK_CORE_CGM_RTC4M0_REF_CFG */

#define BIT_AON_CLK_CORE_CGM_RTC4M0_REF_CFG_CGM_RTC4M0_REF_SEL            BIT(0)

/* REG_AON_CLK_CORE_CGM_RTC4M0_FDK_CFG */

#define BIT_AON_CLK_CORE_CGM_RTC4M0_FDK_CFG_CGM_RTC4M0_FDK_SEL            BIT(0)

/* REG_AON_CLK_CORE_CGM_DJTAG_TCK_CFG */

#define BIT_AON_CLK_CORE_CGM_DJTAG_TCK_CFG_CGM_DJTAG_TCK_PAD_SEL          BIT(16)
#define BIT_AON_CLK_CORE_CGM_DJTAG_TCK_CFG_CGM_DJTAG_TCK_SEL              BIT(0)

/* REG_AON_CLK_CORE_CGM_SP_AHB_CFG */

#define BIT_AON_CLK_CORE_CGM_SP_AHB_CFG_CGM_SP_AHB_DIV(x)                 (((x) & 0x3) << 8)
#define BIT_AON_CLK_CORE_CGM_SP_AHB_CFG_CGM_SP_AHB_SEL(x)                 (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_CA5_TS_CFG */

#define BIT_AON_CLK_CORE_CGM_CA5_TS_CFG_CGM_CA5_TS_SEL(x)                 (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_FUNCDMA_CFG */


/* REG_AON_CLK_CORE_CGM_EMC_REF_CFG */

#define BIT_AON_CLK_CORE_CGM_EMC_REF_CFG_CGM_EMC_REF_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_CSSYS_CFG */

#define BIT_AON_CLK_CORE_CGM_CSSYS_CFG_CGM_CSSYS_DIV(x)                   (((x) & 0x3) << 8)
#define BIT_AON_CLK_CORE_CGM_CSSYS_CFG_CGM_CSSYS_SEL(x)                   (((x) & 0xF))

/* REG_AON_CLK_CORE_CGM_DET_32K_CFG */

#define BIT_AON_CLK_CORE_CGM_DET_32K_CFG_CGM_DET_32K_SEL                  BIT(0)

/* REG_AON_CLK_CORE_CGM_PMU_CFG */

#define BIT_AON_CLK_CORE_CGM_PMU_CFG_CGM_PMU_SEL(x)                       (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_26M_PMU_CFG */

#define BIT_AON_CLK_CORE_CGM_26M_PMU_CFG_CGM_26M_PMU_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_TMR_CFG */

#define BIT_AON_CLK_CORE_CGM_TMR_CFG_CGM_TMR_SEL                          BIT(0)

/* REG_AON_CLK_CORE_CGM_HW_I2C_CFG */

#define BIT_AON_CLK_CORE_CGM_HW_I2C_CFG_CGM_HW_I2C_SEL(x)                 (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SP_I2C0_CFG */

#define BIT_AON_CLK_CORE_CGM_SP_I2C0_CFG_CGM_SP_I2C0_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SP_I2C1_CFG */

#define BIT_AON_CLK_CORE_CGM_SP_I2C1_CFG_CGM_SP_I2C1_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SP_SPI0_CFG */

#define BIT_AON_CLK_CORE_CGM_SP_SPI0_CFG_CGM_SP_SPI0_PAD_SEL              BIT(16)
#define BIT_AON_CLK_CORE_CGM_SP_SPI0_CFG_CGM_SP_SPI0_DIV(x)               (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_SP_SPI0_CFG_CGM_SP_SPI0_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_POWER_CPU_CFG */

#define BIT_AON_CLK_CORE_CGM_POWER_CPU_CFG_CGM_POWER_CPU_SEL(x)           (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_AP_AXI_CFG */

#define BIT_AON_CLK_CORE_CGM_AP_AXI_CFG_CGM_AP_AXI_SEL(x)                 (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_SDIO0_2X_CFG */

#define BIT_AON_CLK_CORE_CGM_SDIO0_2X_CFG_CGM_SDIO0_2X_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SDIO0_1X_CFG */


/* REG_AON_CLK_CORE_CGM_SDIO1_2X_CFG */

#define BIT_AON_CLK_CORE_CGM_SDIO1_2X_CFG_CGM_SDIO1_2X_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SDIO1_1X_CFG */


/* REG_AON_CLK_CORE_CGM_SDIO2_2X_CFG */

#define BIT_AON_CLK_CORE_CGM_SDIO2_2X_CFG_CGM_SDIO2_2X_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_SDIO2_1X_CFG */


/* REG_AON_CLK_CORE_CGM_EMMC_2X_CFG */

#define BIT_AON_CLK_CORE_CGM_EMMC_2X_CFG_CGM_EMMC_2X_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_EMMC_1X_CFG */


/* REG_AON_CLK_CORE_CGM_NANDC_2X_CFG */

#define BIT_AON_CLK_CORE_CGM_NANDC_2X_CFG_CGM_NANDC_2X_DIV(x)             (((x) & 0xF) << 8)
#define BIT_AON_CLK_CORE_CGM_NANDC_2X_CFG_CGM_NANDC_2X_SEL(x)             (((x) & 0xF))

/* REG_AON_CLK_CORE_CGM_NANDC_1X_CFG */

#define BIT_AON_CLK_CORE_CGM_NANDC_1X_CFG_CGM_NANDC_1X_DIV                BIT(8)

/* REG_AON_CLK_CORE_CGM_DPU_CFG */

#define BIT_AON_CLK_CORE_CGM_DPU_CFG_CGM_DPU_SEL(x)                       (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_DPU_DPI_CFG */

#define BIT_AON_CLK_CORE_CGM_DPU_DPI_CFG_CGM_DPU_DPI_DIV(x)               (((x) & 0xF) << 8)
#define BIT_AON_CLK_CORE_CGM_DPU_DPI_CFG_CGM_DPU_DPI_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_DSI_RXESC_CFG */


/* REG_AON_CLK_CORE_CGM_DSI_LANEBYTE_CFG */


/* REG_AON_CLK_CORE_CGM_WCDMA_CFG */

#define BIT_AON_CLK_CORE_CGM_WCDMA_CFG_CGM_WCDMA_SEL                      BIT(0)

/* REG_AON_CLK_CORE_CGM_OTG_REF_CFG */

#define BIT_AON_CLK_CORE_CGM_OTG_REF_CFG_CGM_OTG_REF_SEL                  BIT(0)

/* REG_AON_CLK_CORE_CGM_CPHY_CFG_CFG */

#define BIT_AON_CLK_CORE_CGM_CPHY_CFG_CFG_CGM_CPHY_CFG_SEL                BIT(0)

/* REG_AON_CLK_CORE_CGM_DPHY_REF_CFG */

#define BIT_AON_CLK_CORE_CGM_DPHY_REF_CFG_CGM_DPHY_REF_SEL                BIT(0)

/* REG_AON_CLK_CORE_CGM_DPHY_CFG_CFG */

#define BIT_AON_CLK_CORE_CGM_DPHY_CFG_CFG_CGM_DPHY_CFG_SEL                BIT(0)

/* REG_AON_CLK_CORE_CGM_DSI_TEST_CFG */


/* REG_AON_CLK_CORE_CGM_RFTI_SBI_CFG */

#define BIT_AON_CLK_CORE_CGM_RFTI_SBI_CFG_CGM_RFTI_SBI_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_RFTI1_XO_CFG */

#define BIT_AON_CLK_CORE_CGM_RFTI1_XO_CFG_CGM_RFTI1_XO_SEL                BIT(0)

/* REG_AON_CLK_CORE_CGM_RFTI_LTH_CFG */

#define BIT_AON_CLK_CORE_CGM_RFTI_LTH_CFG_CGM_RFTI_LTH_SEL                BIT(0)

/* REG_AON_CLK_CORE_CGM_RFTI2_XO_CFG */

#define BIT_AON_CLK_CORE_CGM_RFTI2_XO_CFG_CGM_RFTI2_XO_SEL                BIT(0)

/* REG_AON_CLK_CORE_CGM_LVDSRF_CALI_CFG */

#define BIT_AON_CLK_CORE_CGM_LVDSRF_CALI_CFG_CGM_LVDSRF_CALI_SEL          BIT(0)

/* REG_AON_CLK_CORE_CGM_SERDES_DPHY_APB_CFG */

#define BIT_AON_CLK_CORE_CGM_SERDES_DPHY_APB_CFG_CGM_SERDES_DPHY_APB_SEL  BIT(0)

/* REG_AON_CLK_CORE_CGM_SERDES_DPHY_REF_CFG */

#define BIT_AON_CLK_CORE_CGM_SERDES_DPHY_REF_CFG_CGM_SERDES_DPHY_REF_SEL  BIT(0)

/* REG_AON_CLK_CORE_CGM_SERDES_DPHY_CFG_CFG */

#define BIT_AON_CLK_CORE_CGM_SERDES_DPHY_CFG_CFG_CGM_SERDES_DPHY_CFG_SEL  BIT(0)

/* REG_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG */

#define BIT_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG_CGM_ANALOG_IO_APB_DIV(x)   (((x) & 0x3) << 8)
#define BIT_AON_CLK_CORE_CGM_ANALOG_IO_APB_CFG_CGM_ANALOG_IO_APB_SEL(x)   (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_DJTAG_TCK_HW_CFG */


/* REG_AON_CLK_CORE_CGM_GPU_CORE_CFG */

#define BIT_AON_CLK_CORE_CGM_GPU_CORE_CFG_CGM_GPU_CORE_DIV(x)             (((x) & 0x3) << 8)
#define BIT_AON_CLK_CORE_CGM_GPU_CORE_CFG_CGM_GPU_CORE_SEL(x)             (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_GPU_SOC_CFG */

#define BIT_AON_CLK_CORE_CGM_GPU_SOC_CFG_CGM_GPU_SOC_DIV(x)               (((x) & 0x3) << 8)
#define BIT_AON_CLK_CORE_CGM_GPU_SOC_CFG_CGM_GPU_SOC_SEL(x)               (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_WCN_CFG */

#define BIT_AON_CLK_CORE_CGM_WCN_CFG_CGM_WCN_DIV(x)                       (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_WCN_CFG_CGM_WCN_SEL(x)                       (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_MM_EMC_CFG */

#define BIT_AON_CLK_CORE_CGM_MM_EMC_CFG_CGM_MM_EMC_SEL(x)                 (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_MM_AHB_CFG */

#define BIT_AON_CLK_CORE_CGM_MM_AHB_CFG_CGM_MM_AHB_SEL(x)                 (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_BPC_CFG */

#define BIT_AON_CLK_CORE_CGM_BPC_CFG_CGM_BPC_SEL(x)                       (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_DCAM_IF_CFG */

#define BIT_AON_CLK_CORE_CGM_DCAM_IF_CFG_CGM_DCAM_IF_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_ISP_CFG */

#define BIT_AON_CLK_CORE_CGM_ISP_CFG_CGM_ISP_SEL(x)                       (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_JPG_CFG */

#define BIT_AON_CLK_CORE_CGM_JPG_CFG_CGM_JPG_SEL(x)                       (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_CPP_CFG */

#define BIT_AON_CLK_CORE_CGM_CPP_CFG_CGM_CPP_SEL(x)                       (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_SENSOR0_CFG */

#define BIT_AON_CLK_CORE_CGM_SENSOR0_CFG_CGM_SENSOR0_DIV(x)               (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_SENSOR0_CFG_CGM_SENSOR0_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_SENSOR1_CFG */

#define BIT_AON_CLK_CORE_CGM_SENSOR1_CFG_CGM_SENSOR1_DIV(x)               (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_SENSOR1_CFG_CGM_SENSOR1_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_SENSOR2_CFG */

#define BIT_AON_CLK_CORE_CGM_SENSOR2_CFG_CGM_SENSOR2_DIV(x)               (((x) & 0x7) << 8)
#define BIT_AON_CLK_CORE_CGM_SENSOR2_CFG_CGM_SENSOR2_SEL(x)               (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_MM_VSP_EMC_CFG */

#define BIT_AON_CLK_CORE_CGM_MM_VSP_EMC_CFG_CGM_MM_VSP_EMC_SEL(x)         (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_MM_VSP_AHB_CFG */

#define BIT_AON_CLK_CORE_CGM_MM_VSP_AHB_CFG_CGM_MM_VSP_AHB_SEL(x)         (((x) & 0x3))

/* REG_AON_CLK_CORE_CGM_VSP_CFG */

#define BIT_AON_CLK_CORE_CGM_VSP_CFG_CGM_VSP_SEL(x)                       (((x) & 0x7))

/* REG_AON_CLK_CORE_CGM_GPU_CORE_FRA_DIV */

#define BIT_AON_CLK_CORE_CGM_GPU_CORE_FRA_DIV_CGM_GPU_CORE_FRA_DIV(x)     (((x) & 0xF))

/* REG_AON_CLK_CORE_CGM_GPU_SOC_FRA_DIV */

#define BIT_AON_CLK_CORE_CGM_GPU_SOC_FRA_DIV_CGM_GPU_SOC_FRA_DIV(x)       (((x) & 0xF))


#endif /* AON_CLK_CORE_H */

